![]() ![]() Variations in the threshold voltage stem from complex interfacial instability phenomena, such as near-interfacial oxide trap charging. Its attributes include delivering great performance at high fields and high temperatures, but operating in this manner makes the device susceptible to bias- and temperature-induced instability of the threshold voltage. One of the wide bandgap power devices that is growing in revenue, and will continue to do so, is the SiC MOSFET. The CnCV technique offers excellent repeatability and matching to mercury probe for epitaxially grown SiC and GaN (see Figure 3). Primary applications for the CnCV technique include dopant concentration measurements and dopant depth profiling. Applications of the CnCV technique to wide bandgap materials. Armed with all this information, engineers can gain great insight into the nature of their wide bandgap material and devices. These characteristics form a basis for quantification of the semiconductor, interface and dielectric parameters. By adopting this approach, the technique provides a full set of data including voltage, charge, capacitance and surface barrier voltage, as well as plots of V-Q, C-Q and C-V. ![]() In a corona charge bias sweep, the semiconductor space charge and the surface barrier are cycled between accumulation and depletion. The non-contact capacitance is calculated by dividing the change in charge by the change in voltage. These charge increments induce a change in surface voltage, which is measured in a non-contact manner, using a vibrating Kelvin probe (see Figure 1). These charges- they may be positive or negative, depending on the selected discharge polarity - are gently deposited on the surface of the wide bandgap semiconductor or dielectric in known charging increments. In CnCV metrology, electric charge that is needed for bias is provided by corona discharge in air. Our tool helps them in this endeavour - all of the parameters that are listed in Table 1 can be measured very precisely, at selected locations on a wafer, with results displayed as contour maps that reveal process uniformity. This enables them to evaluate process uniformity and identify localised defects. To control the semiconductor manufacturing process, engineers must map the wafer surface. Its capabilities include dopant concentration profiling of GaN and SiC, measuring the two-dimensional electron-gas sheet charge in an AlGaN/GaN HEMT, and characterisation of interfaces between dielectrics and wide bandgap semiconductors (for a broader list of capabilities, see Table 1). In response to broadening interest from the wide bandgap community, our team at Semilab SDI, based in Tampa, FL, has introduced the CnCV 200 series of tools. Semilab SDI CnCV 230 tool for non-contact C-V characterisation of wide bandgap semiconductors. Recently, however, the use of this technique has expanded, so that it can start to serve the wide bandgap power and RF industries through characterisation of SiC, GaN and Ga 2O 3 based materials. More than 400 of these tools have been installed worldwide, used primarily for dielectric characterisation. It is a proven, production-tested method that has been widely adopted in silicon fabs since the 1990s. It offers a non-destructive, preparation-free alternative to standard C-V that trims manufacturing costs, while slashing the time for data feedback from weeks to just minutes.ĬnCV is based on the corona-Kelvin technique that is not new. To address these issues, the industry needs a non-destructive, cost-effective form of C-V metrology that provides rapid feedback for device development and manufacturing process control.įulfilling all of these requirements is advanced corona-based non-contact C-V (CnCV) metrology, developed for comprehensive C-V characterisation of wide bandgap semiconductors, dielectrics and interfaces. An additional downside with standard C-V is that it is a destructive test, preventing the use of monitor wafers in subsequent production. When devices are being developed, this slows progress and when C-V is used to monitor a manufacturing process, it takes longer for issues to be identified, compromising yield. There is a cost associated with fabricating electrical test structures, and feedback can take weeks. Standard C-V measurements are well-established, but have significant drawbacks. One of these key techniques is capacitance-voltage (C-V), which provides important information such as dopant concentration, as well as dielectric and interfacial properties. To carry this out, foundries and chip manufacturers have dedicated metrology tools that offer a wide variety of characterisation techniques. Material AND DEVICE characterisation is an essential step in the production of compound semiconductor devices.
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